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Distributed transactions

Table of contents [ hide ] Basic theory  CAP States that any distributed data store can provide only two of the following three guarantees. Consistency Every read receives the most recent write or an error. Availability Every request receives a (non-error) response, without the guarantee that it contains the most recent write. Partition tolerance The system continues to operate despite an arbitrary number of messages being dropped (or delayed) by the network between nodes. Typical architecture of distributed systems When a network partition failure happens, it must be decided  whether to do one of the following: CP: cancel the operation and thus decrease the availability but ensure consistency AP: proceed with the operation and thus provide availability but risk inconsistency. BASE Basically-available, soft-state, eventual consistency. Base theory is the practical application of CAP theory, that is, under the premise of the existence of partitions and copies, through certain syste

I/O system

I/O hardware

  • Port: a connection point between I/O devices and the host.
    • E.g.: user ports.
  • Bus: a set of wires and a well-defined protocol that specifies messages sent over the wires.
    • E.g.: PCI bus.
  • Controller: a collection of electronics that can operate a port, a bus, or a device.
    • A controller could have its own processor and memory. Etc. (e.g.: SCSI controller).

Basic I/O Method (Port-mapped I/O)

  • Each I/O port (device) is identified by the unique port address.
  • Each I/O port consists of four registers (1~4bytes).
    • Data-in register: read by the host to get input
    • Data-out register: written by the host to send output
    • Status register: read by the host to check I/O status
    • Control register: written by the host to control the device
  • The program interacts with an I/O port through special I/O instructions (different from mem. access).
    • X86: IN, OUT

I/O methods Categorization

  • Depending on how to address a device:
    • Port-mapped I/O.
      • Use different address spaces for memory.
      • Access by special I/O instruction (e.g. IN, OUT).
    • Memory-mapped I/O.
      • Reserve specific memory space for the device.
      • Access by standard data-transfer instruction (e.g. MOV).
      • Good: 
        • More efficient for large memory I/O (e.g. graphic card).
      • Bad:
        • Vulnerable to accident modification error.
  • Depending on how to interact with the device:
    • Poll(busy-waiting): processor periodically checks the status register of a device
    • Interrupt: device notifies the processor of its completion
  • Depending on who controls the transfer:
    • Programmed I/O: transfer controlled by CPU.
    • Direct memory access(DMA) I/O: controlled by a DMA controller (a special purpose controller).
      • Design for large data transfer.
      • Commonly used with memory-mapped I/O and interrupt.

I/O subsystem

  • I/O Scheduling - improve system performance by ordering the jobs in the I/O queue.
    • E.g. disk I/O order scheduling.
  • Buffering - store data in memory while transferring between I/O devices.
    • Speed mismatch between I/O devices.
    • Devices with different data-transfer sizes.
    • Support copy semantics.
  • Caching - fast memory that holds copies of data.
    • Always just a copy.
    • Key to performance.
  • Spooling - holds output for a device.
    • E.g. printing (cannot accept interleaved files).
  • Error handling - when an I/O error happens.
    • E.g. SCSI devices return error information.
  • I/O protection
    • Privilege instructions.

Blocking and Nonblocking I/O

  • Blocking: process suspended until I/O completed
    • Easy to use and understand
    • Insufficient for some needs 
    • Use for synchronous communication & I/O
  • Nonblocking
    • Implemented via multi-threading
    • Returns quickly with the count of bytes read or written
    • Use for asynchronous communication & I/O

Performance

  • I/O is a major in system performance.
  • It places heavy demands on the CPU to execute device driver code.
  • The resulting context switches stress the CPU and its hardware caches.
  • I/O loads down the memory bus during data copy between controllers and physical memory.
  • Interrupt handling is a relatively expensive task.
    • Busy waiting could be more efficient than interrupt-driven if I/O time is small.

Improving performance

  • Reduce the number of context switches
  • Reduce data copying
  • Reduce interrupts by using large transfers, smart controllers, polling
  • Use DMA
  • Balance CPU, memory, bus, and I/O performance for highest throughput
reference:
https://www.amazon.com/-/zh_TW/Operating-System-Concepts-Abraham-Silberschatz/dp/1119800366/ref=sr_1_1?keywords=Operating-System-Concepts&qid=1669538704&s=books&sr=1-1

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